View EN5312QI_8818498.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

enpirion ? power datasheet EN5312QI 1a powersoc synchronous buck regulator with integrated inductor *optimized pcb layout file downloadable from the enpirion website to assure first pass design success. featuring integrated inductor technology voltage select dac switch vref (+) (-) error amp v sense v fb v out vs0 vs1 vs2 package boundry p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+) (-) pwm comp v in enable gnd logic compensation network product highlights ? revolutionary integrated inductor ? 5mm x 4mm x1.1mm qfn package ? very small total solution foot print* ? 4 mhz switching frequency ? only two low cost mlcc caps required ? designed for low noise/low emi ? very low ripple voltage; 5mv p-p typical ? high efficiency, up to 95% ? wide 2.4v to 6.6v input range ? 1000ma continuous output current ? less than 1 a standby current. ? excellent transient performance ? 3 pin vid output voltage select ? external divider: 0.6v to v in -v dropout ? 100% duty cycle capable ? short circuit and over current protection ? uvlo and thermal protection ? rohs compliant; msl 3 260c reflow product overview the ultra - low - profile en5312 qi is targeted to applications where board area and profile are critical. en5312 qi is a complete power conversion solution requiring only two low cost ceramic mlcc caps. inductor, mosfets, pwm, and compensation are int egrated into a tiny 5mm x 4mm x 1.1mm qfn package. the en5312 qi is engineered to simplify design and to minimize layout constraints. 4 mhz switching frequency and internal type iii compensation provides superior transient response. w ith a 1.1 mm profile , the en5312 qi is ideal for space and height constrained applications. a 3 - pin vid output voltage selector provides seven pre - programmed output voltages along with an option for external resistor divider. output voltage can be programmed on - the - fly to pr ovide fast, dynamic voltage scaling. typical application circuit v in v sense v in v s1 v s2 v s0 EN5312QI 10f 4.7 f v out v out gnd enable v fb voltage select figure 1 . typical application circuit. applications ? area constrained applications ? noise sensitive applications such as a/v and rf ? ldo replacement for improved thermals ? lower power fpga and asics ? smart phones , pdas ? voip and video phones ? personal media players 04535 december 14, 2015 rev e
EN5312QI 2 www.altera.com/enpirion pin description v in (pin 1,2): input voltage pin. supplies power to the ic. input gnd : (pin 3): input power ground. connect this pin to the ground terminal of the input capacitor. refer to layout recommendations for further details. output gnd : (pin 4): power ground. the output filter capacitor should be connected between this pin and v out . refer to layout recommendations for further detail. v out (pin 5,6,7): regulated output voltage. nc (pin 8,9,10,11,12,13,14): these pins should not be electrically connected to each other or to any external signal, voltage, or ground. one or more of these pins may be connected internally. v sense (pin 15): sense pin for output voltage regulation. connect v s ense to the output voltage rail as close to the terminal of the output filter capacitor as possible. v fb (pin 16): feedback pin for external divider option. when using the external divider option (vs0=vs1=vs2= high) connect this pin to the center of the external divider. set the divider such that v fb = 0.603v. vs0,vs1,vs2 (pin 17,18,19): output voltage select. vs0=pin19, vs1=pin18, vs2=pin17. selects one of seven preset output voltages or choose external divider by connecting pins to logic high or low. logic low is defined as v low 0.4v. logic high is defined as v high 1.4v. any level between these two values is indeterminate. enable (pin 20): output enable. enable = logic high, disable = logic low. logic low is defined as v low 0.2v. logic hi gh is defined as v high 1.4v. any level between these two values is indeterminate. bottom thermal pad : device thermal pad to remove heat from package. connect to pcb surface ground pad and pcb internal ground plane (see layout recommendations). figure 2. pin description, top view. 04535 december 14, 2015 rev e
EN5312QI 3 www.altera.com/enpirion functional block diagram voltage select dac switch vref (+) (-) error amp v sense v fb v out vs0 vs1 vs2 package boundry p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+) (-) pwm comp v in enable gnd logic compensation network figure 3. functional block diagram. 04535 december 14, 2015 rev e
EN5312QI 4 www.altera.com/enpirion absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond recommended operating conditions is not implied. stress beyond absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated cond itions for extended periods may affect device reliability. parameter symbol min max units input supply voltage v in - 0.3 7.0 v voltages on: enable, v sense , v s0 - v s2 - 0.3 v in + 0.3 v voltage on: v fb - 0.3 2.7 v storage temperature range t stg - 65 150 c reflow temp, 10 sec, msl3 jedec j - std - 020a 260 c esd rating (based on human body model) 2000 v recommended operating conditions parameter symbol min max units input voltage range (vid) v in 2.4 5.5 v input voltage range (external divider (vfb) ) 1 v in 2.4 6.6 v output voltage range v out 0.6 v in - 0.6 v output current i out 0 1000 ma operating ambient temperature t a - 40 +85 c operating junction temperature t j - 40 +125 c 1. see section ?application information? for s pecific c ircuit r equirements thermal characteristics parameter symbol typ units thermal resistance: junction to ambient (0 lfm) 04535 december 14, 2015 rev e
EN5312QI 5 www.altera.com/enpirion el ectrical characteristics note: t a = 25c unless otherwise noted. typical values are at v in = 3.6v, c in = 4.7 f, c out =10 f. note: v in must be greater than v out + 0.6v. parameter symbol test conditions min typ max units operating input voltage v in using vid 2.4 5.5 v using external divider (vfb) 1 2.4 6.6 v under voltage lockout v uvlo v in going low to high 2.2 2.3 v uvlo hysteresis 0.145 v v out initial accuracy (vid) v out 9?9 in ? 5.5 v, i load = 100ma; t a = 25c - 2.0 +2.0 % v out variation for all causes (vid) v out 9?9 in ? 5.5 v, i load = 0 - 1a, t a = - 40c to +85c - 3.0 +3.0 % feedback pin voltage v fb 9?9 in ? 6.6 v, i load = 100ma ta = 25c; vso=vs1=vs2=1 0.591 0.603 0.615 v feedback pin voltage v fb 9?9 in ? 6.6 v, i load = 0 - 1a, t a = - 40c to +85c; vso=vs1=vs2=1 0.585 0.603 0.621 v feedback pin input current i fb 1 na dynamic voltage slew rate ? v slew 1.24 1.65 2.1 v/ms output current i out 1000 ma shut - down current i sd enable = low 0.75 ? ? ? soft - start operation v out soft start slew rate ? ? ? 04535 december 14, 2015 rev e
EN5312QI 6 www.altera.com/enpirion typical performance characteristics top to bottom: v out = 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v, 0.8 v top to bottom: v out = 2.5 v, 1.8 v, 1.5 v, 1.2 v, 0.8 v output ripple : v in = 5.0 v output ripple : v in = 3.3 v v out = 1.2v, i load = 1a , c out = 1 x 10f 0805 v out = 1.2v, i load = 1a, c out = 1 x 10f 0805 efficiency vs. load current (vin = 5.0v) 50 55 60 65 70 75 80 85 90 95 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 load current (a) efficency (%) efficiency vs. load current (vin = 3.3v) 50 55 60 65 70 75 80 85 90 95 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 load current (a) efficency (%) 04535 december 14, 2015 rev e
EN5312QI 7 www.altera.com/enpirion detailed description functional overview the en5312 qi is a complete dcdc converter solution requiring only two low cost mlcc capacitors. mosfet switches, pwm controller, gate - drive, compensation, and inductor are integrated into the tiny 5mm x 4mm x 1.1mm package to provide the smallest footprint possible while maintaining high efficiency, low ripple, and high performance. the converter uses voltage mode control to provide the simplest implementation and high noise immunity. the device operates at a high switching frequency. the high switching frequency allows for a wide control loop bandwidth providing excellent transient performance. the high switching fre quency enables the use of very small components making possible this unprecedented level of integration. altera ?s enpirion proprietary power mosfet technology provides very low switching loss at frequencies of 4 mhz and higher, allowing for the use of very small internal components, and very wide control loop bandwidth. unique magnetic design allows for integration of the inductor into the very low profile 1.1mm package. integration of the inductor virtually eliminates the design/layout issues normally a ssociated with switch - mode dcdc converters. all of this enables much easier and faster integration into various applications to meet demanding emi requirements. output voltage is chosen from seven preset values via a three pin vid voltage select scheme. an external divider option enables the selection of any voltage in the 0.6v to v in - 0.6v range. this reduces the number of components that must be qualified and reduces inventory burden. the vid pins can be toggled on the fly to implement glitch free dyna mic voltage scaling. protection features include under - voltage lock - out (uvlo), over - current protection (ocp), short circuit protection, and thermal overload protection. integrated inductor altera has introduced the world?s first product family featuring integrated inductors. the use of an internal inductor localizes the noises associated with the output loop currents. the inherent shielding and compact construction of the integrated inductor reduces the radiated noise that couples into the traces of the circuit board. further, the package layout is optimized to reduce the electrical path length for the ac ripple currents that are a major source of radiated emissions from dcdc converters. the integrated inductor significantly reduces parasiti c effects that can harm loop stability, and makes layout very simple. soft start internal soft start circuits limit in - rush current when the device starts up from a power down condition or when the ?enable? pin is asserted ?high?. digital control circuit ry limits the v out ramp rate to levels that are safe for the power mosfets and the integrated inductor. the en5312 qi operates in a constant slew rate when the output voltage is programmed with an internal vid code. the en5312 qi, when in external resistor divider mode, has a constant start up time. please refer to the electrical characteristics table for soft - start slew rates and soft - start time excess bulk capacitance on the output of the device can cause an over - current condition at startup. assuming no- load at startup, t he maximum total capacitance on the output , including the output filter capacitor, bulk and decoupling capacitance, at the load, is given as: 04535 december 14, 2015 rev e
EN5312QI 8 www.altera.com/enpirion in vid mode: c out_total_max = c out_filter + c out_bulk = 7 00uf in external divider mode: c out_total_max = 1.22x10 -3 /v out farads the nominal value for c out is 10uf. see the applications section for more details. over current/short circuit protection the current limit function is achieved by sensing the current flowing through a sense p - mosfet which is compared to a reference current. when this level is exceeded the p - fet is turned off and the n - fet is turned on, pulling v out low. this condition is maintained for a period of 1ms and then a normal soft start is initiated. if the over current condition still persists, this cycle will repeat in a ?hick - up? mode. under voltage lockout during initial power up an under voltage lockout circuit will hold - off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. if the voltage drops below the uvlo threshold the lockout circuitry will again disable the switching. hysteresis is included to prevent chattering between states. enable the enable pin provides a means to shut down the converter or enable normal operation. a logic low will disable the converter and cause it to shut down. a logic high will enable the converter into normal operation. in shutdown mode, the device quiescent current will be less than 1 ua. note: this pin must not be left flo ating. thermal shutdown when excessive power is dissipated in the chip, the junction temperature rises. once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. when the junction temperature decreases by 15c , the device will go through the normal startup process. application information output voltage select to provide the highest degree of flexibility in choosing output voltage, the en5312 qi uses a 3 pin vid, or voltage id, output voltage select arrangement. this allows the designer to choose one of seven preset voltages, or to use an external voltage divider. internally, the output of th e vid multiplexer sets the value for the voltage reference dac, which in turn is connected to the non - inverting input of the error amplifier. this allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. table 1 shows the various vs0 - vs2 pin logic states and the associated output voltage levels. a logic ?1? indicates a connection to v in or to a ?high? logic voltage level. a logic ?0? indicates a connection to ground or to a ?low? logic voltage level. these pins can be either hardwired to v in or gnd or alternatively can be driven by standard logic levels. logic low is defined as v low 0.4v. logic high is defined as v high 1.4v. any level between these two values is indeterminate. these pins must not be left floating. the external voltage divider p in, v fb , may be left floating for all vid settings other than the vs0=vs1=vs2= ?1?. 04535 december 14, 2015 rev e
EN5312QI 9 www.altera.com/enpirion vs2 vs1 vs0 v out 0 0 0 3.3v 0 0 1 2.5v 0 1 0 1.8v 0 1 1 1.5v 1 0 0 1.25v 1 0 1 1.2v 1 1 0 0.8v 1 1 1 user selectable external voltage divider as described above, the external voltage divider option is chosen by connecting the vs0, vs1, and vs2 pins to v in or logic ?high?. the en5312 qi uses a separate feedback pin, v fb , when using the external divider. for applications with v in 5.5v, v sense must be connected to v out as indicated in figure 4. figure 5 indicates the required connections for v in > 5.5 v. v in v sense v in v s1 v s2 v s0 EN5312QI 10 p f 4.7 uf v out v out gnd enable ra rb v fb figure 4. external divider (v in d 5.5v ). the output voltage is selected by the following formula: rb ra out v v 1603.0 r a must be chosen as 200k : to maintain loop gain. then r b is given as: : 603.0 102.1 5 out b v x r v out can be programmed over the range of 0.6v to v in ? 0.6v (0.6 is the nominal full load dropout voltage including margin). v in v sense v in v s1 v s2 v s0 EN5312QI 10 p f 4.7 uf v out v out gnd enable ra rb v fb 27pf ca figure 5. external divider ( v in > 5.5 v ). for applications where v in > 5.5v , the v sense connection is not necessary , but the addition of c a = 27pf is required . dynamically adjustable output the en5312 qi is designed to allow for dynamic switching between the predefined vid voltage levels . the inter - voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. the slew rate is identical to the soft - start slew rate of 1.65v/ms. dynamic transitioning between internal vid settings and the external divider is not allowed. input and output capacitors the i nput capacitance requirement is 4.7uf. altera recommends that a low esr mlcc capacitor be used. the input capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielectric formulations lose capacitance with frequency, bi as, and with temperature, and are not table 1 . vid voltage select settings. 04535 december 14, 2015 rev e
EN5312QI 10 www.altera.com/enpirion suitable for switch - mode dc - dc converter input and output filter applications. the output capacitance requirement is a minimum of 10uf. the control loop is designed to be stable with up to 60uf of total output cap acitance next to the output pins of the device without requiring modification to the compensation network. v out has to be sensed at the last output filter capacitor next to the device . capacitance above the 10uf minimum should be added if the transient performance is not sufficient using the 10uf. altera recommends a low esr mlcc type capacitor be used. additional bulk capacitance for decoupling and bypass can be placed at the load as long as there is sufficient separation between the v out sense point and the bulk capacitance. the separation provides an inductance that isolates the control loop from the bulk capacitance. excess total capacitance on the output (output filter + bulk) c an cause an over - current condition at startup. refer to the section on soft - start for the maximum total capacitance on the output. the output capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch - mode dc - dc converter input and output filter applications. power-up sequencing during power - up, enable should not be asserted before vin . tying these pins together meets these requirements. startup into p re -bias the en53 12 qi does not support startup into a pre - biased output. the output of the en5 3 12qi can not be pre - biased with a voltage when it is first enabled. 1. for v in cin manufacturer part # value wvdc case size murata grm219r61a475ke19d 4.7uf 10v 0805 grm319r61a475ka01d 4.7uf 10v 1206 grm219r60j475ke01d 4.7uf 10v 0805 grm31mr60j475ka01l 4.7uf 10v 1206 panasonic ecj-2fb1a475k 4.7uf 10v 0805 ecj-3yb1a475k 4.7uf 10v 1206 ecj-2fb0j475k 4.7uf 6.3v 0805 ecj-3yb0j475k 4.7uf 6.3v 1206 taiyo yuden lmk212bj475kg-t 4.7uf 10v 0805 lmk316bj475kd-t 4.7uf 10v 1206 jmk212bj475kd-t 4.7uf 6.3v 0805 cout manufacturer part # value wvdc case size murata grm219r60j106ke19d 10uf 6.3v 0805 grm319r60j106ke01d 10uf 6.3v 1206 panasonic ecj-2fb0j106k 10uf 6.3v 0805 ecj-3yb0j106k 10uf 6.3v 1206 taiyo yuden jmk212bj106kd-t 10uf 6.3v 0805 jmk316bj106kf-t 10uf 6.3v 1206 1 1 1 04535 december 14, 2015 rev e
EN5312QI 11 www.altera.com/enpirion layout considerations* *optimized pcb layout file downloadable from the altera w ebsite to assure first pass design success. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the en5312 qi package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the en5312 qi sho uld be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2 : do not connect gnd pins 3 and 4 together. pin 3 should be used for the input capacitor local ground and pin 4 should be used for the output capacitor ground. the ground pad for the input and output filter capacitors should be isolated ground islands and should be connected to system ground as indicated in recommendation 3 and recommendation 5. recommendation 3 : multi ple small vias (0.25mm after copper plating) should be used to connect ground terminals of the input capacitor and the output capacitor to the system ground plane. this provides a low inductance path for the high - frequency ac currents; thereby reducing ri pple and suppressing emi (see fig. 6, fig. 7, and fig. 8 ). recommendation 4 : the large thermal pad underneath the component must be connected to the system ground plane through as many thermal vias as possible. the vias should use 0.33mm drill size with m inimum one ounce copper plating (0.035mm plating thickness). this provides the path for heat dissipation from the converter. recommendation 5: the system ground plane referred to in recommendations 3 and 4 should be the first layer immediately below the surface layer (pcb layer 2). this ground plane should be continuous and un - interrupted below the converter and the input and output capacitors that carry large ac currents. if it is not possible to make pcb layer 2 a continuous ground plane, an uninterr upted ground ?island? should be created on pcb layer 2 immediately underneath the en5312 qi and its input and output capacitors. the vias that connect the input and output capacitor grounds, and the thermal pad to the ground island, should continue through to the pcb gnd layer as well. recommendation 6 : as with any switch - mode dc/dc converter, do not run sensitive signal or control lines underneath the converter package. recommendation 7 : the vout sense point should be just after the last output filter ca pacitor next to the device. keep the sense trace short in order to avoid noise coupling into the node. recommendation 8 : keep r a , c a , and r b close to the vfb pin (see figures 4 and 5 ). the vfb pin is a high - impedance, sensitive node. keep the trace to this pin as short as possible. whenever possible, connect r b directly to the gnd pin instead of going through the gnd plane. fig ure 6 shows an example schematic for the en5312 qi using the internal voltage select. in thi s example, the device is set to a v ou t of 1.5v (vs2=0, vs1=1, vs0=1). figure 7 shows an example schematic using an external voltage divider. vs0=vs1=vs2= ?1?. the resistor values are chosen to give an output voltage of 2.6v. 04535 december 14, 2015 rev e
EN5312QI 12 www.altera.com/enpirion figure 6 . example applicat ion, vout=1.5v. figure 7 . example application, external divider, vout = 2.6v. figure 8 shows an example board layout. the left side of the figure demonstrates construction of the pcb top layer. note the placement of the vias from the input and output filter capacitor grounds, and the thermal pad, to the pcb ground on layer 2 (1 st layer below pcb surface). the right side of the figure shows the layout with the components populated. note the placement of the vias per recommendation 3. figure 8 . example layout showing pcb top layer, as well as demonstrating use of vias from input, output filter capacitor local grounds, and thermal pad, to pcb system ground. v out nc nc nc v out v fb v sense nc nc nc nc v out gnd gnd v in enable vs0 vs1 vs2 1 2 6 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in 4.7uf 10 f v in v out (see layout recommendation 3) v out nc nc nc v out v fb v sense nc nc nc nc v out gnd gnd v in enable vs0 vs1 vs2 1 2 6 5 4 3 10 9 8 7 11 12 13 14 15 16 20 19 18 17 v in 4.7uf 10 f v in v out ra=200k rb=60k (see layout recommendation 3) 04535 december 14, 2015 rev e
EN5312QI 13 www.altera.com/enpirion design considerations for lead- frame based modules exposed metal on bottom o f package altera has developed a break - through in package technology that utilizes the lead frame as part of the electrical circuit. the lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, it does require some special considerations. as part of the package assembly process, lead frame construction requires that for mechanical support, some of the lead - frame cantilevers be exposed at the point where wire - bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package. only the large thermal pad and the perimeter pin pads are to be mechanically or electrically connected to the pc board. the pcb top layer under the en5312 qi should be clear of any metal except for the large thermal pad. the ?grayed - out? area in figure 9 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the pcb. note: clearance between the various exposed metal pads, the thermal ground pad, and the perimeter pins, meets or exceeds jedec requirements for lead frame package construction (jedec mo - 220, issue j, date may 2005). the separation between the large thermal pad and the nearest adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. this is shown in figure 10 . figure 9 . exposed metal and mechanical dimensions of the package. gray area represents bottom metal no - connect and area that should be clear of any traces, planes, or vias, on the top layer of the pcb. thermal pad. connect to ground plane 04535 december 14, 2015 rev e
EN5312QI 14 www.altera.com/enpirion figure 10 . exposed pad clearances; altera?s enpirion lead frame package complies with jedec requirements. figure 1 1 . recommended solder mask opening. 04535 december 14, 2015 rev e
EN5312QI 15 www.altera.com/enpirion figure 1 2 . package mechanical dimensions. ordering information part number temp range package en5312 qi - 40 04535 december 14, 2015 rev e
EN5312QI 16 www.altera.com/enpirion contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408 - 544 - 7000 www.altera.com ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in acco rdance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 04535 december 14, 2015 rev e

▲Up To Search▲

Price & Availability of EN5312QI

	To Download EN5312QI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .